Advancing semiconductor tech, one nanometer at a time

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Dr. Griselda Bonilla is the Senior Manager of the Advanced BEOL Interconnect Technology team at IBM Research, responsible for delivering innovative solutions that advance IBM’s industry-leading, on-chip interconnect (BEOL) technologies. We sat down with her before her team gave two talks at the IITC/AMC Conference in San Jose, California this week.

First off, tell us a bit about why 7nm technology is such a big deal.

Dr. Griselda Bonilla (Photo: NACME)

Dr. Griselda Bonilla, Senior Manager of the Advanced BEOL Interconnect Technology team, IBM Research (Photo: NACME)

Griselda Bonilla: 7nm technology will be crucial to future advances across a number of platform and systems, including cloud computing, big data, cognitive computing, and mobile. As part of our $3 billon investment in 2014 and alliance with New York State, GLOBALFOUNDRIES, and Samsung, the techniques and scaling improvements we have developed could result in a 50 percent power/performance improvement for these next generation systems. The 7nm node achievement we have made, through a combination of new materials, tools, and techniques, is very promising.

What was your role in last year’s breakthrough 7nm node test chip?

GB: I managed a large, cross-functional team that defined and developed a new and reliable interconnect technology at 36nm pitch.

What has the progress been like since last year’s breakthrough?

GB: It’s been exciting. BEOL scaling is a big challenge for recent CMOS nodes, including the 7nm that we’ve been working on. We have focused on back-end-of-line interconnects that connect devices – transistors, capacitors, resistors, and so on – to each other. The copper (Cu) wiring we are working with is less than 1/20th the size of the original Cu interconnects introduced nearly 20 years ago. We have demonstrated, for the first time, aggressively scaled interconnects using extreme ultraviolet (EUV) lithography, which allows for flexibility in circuit designs. This is significant in part because other patterning approaches are increasingly complex, and therefore impose restrictions on the circuit designs.

Tell us about the IITC/AMC Conference. What are you presenting, and why is this the place to introduce your work?

GB: The conference is the premier BEOL gathering of the year. Key industrial and academic participants get together to share and discuss the latest developments. We were invited to give two talks on 7nm BEOL Technology and BEOL Design Technology Co-Optimization for Beyond 7nm Technology. My colleague, Dr. Theo Standaert, is the lead author on our 7nm BEOL technology paper. His team is in charge of defining and demonstrating interconnect solutions for future technology nodes.

We also have six contributed talks and four posters covering key BEOL performance metrics and novel integration methods and materials. The IBM Research Alliance has the most papers and talks at this year’s conference.

Tell us more about the Alliance. How have GLOBALFOUNDRIES, SUNY Polytechnic Institute, and the other partners contributed?

GB: These partnerships have been key. They have helped enable the exploration of the latest BEOL innovations through a unique collaboration of the deep research expertise of IBM, the development and manufacturing skill of GLOBALFOUNDRIES and Samsung,

Close up of IBM 7nm node test chip produced at SUNY Poly CNSE in Albany, NY. (Darryl Bautista/Feature Photo Service for IBM)

Close-up of IBM 7nm node test chip produced at SUNY Poly CNSE in Albany, NY. (Darryl Bautista/Feature Photo Service for IBM)

and the academic innovation and leadership of SUNY Poly.

SiGe channel material and EUV lithography were pinpointed as breakthroughs last year. What are the new complementary materials or techniques being employed now?

GB: We plan to highlight the introduction of cobalt metallization at the contact level, and the technical details of the required innovations to make a reliable BEOL interconnect at these really exciting, aggressive dimensions.

What do these advancements mean in terms of being able to mass produce a 7nm chip?

GB: They enable interconnect scaling to continue into the 7nm technology node, with demonstrated yield and reliability. We’ll be presenting an industry-first, full evaluation of breakthrough contact/local interconnect metallurgies, aimed at breakthrough contact resistance reductions – about 2.5x lower. These high resistances have emerged as severe performance-limiters for high-end CMOS Ultra-Large-Scale-Integration (ULSI) in 10nm and 7nm technology nodes.

What is the significance of the local interconnects breakthrough?

GB: We made the first change to contact metallurgy since the inception of damascene processing – a unique, additive processing technique used to form the Cu interconnects, analogous to the metal inlay techniques used in the Middle Ages – some 25 years ago. This change will be critical for 7nm node technology, since it provides a real path to mitigate the performance loss with the traditional metal – tungsten.