Scientists at Oak Ridge National Laboratory and Hypres, a digital superconductor company, have tested a novel cryogenic, or low-temperature, memory cell circuit design that may boost memory storage while using less energy in future exascale and quantum computing applications. The team used Josephson junctions made from niobium and aluminum-based materials, fabricated at Hypres, for the single-bit memory design on a chip and demonstrated write, read and reset memory operations occurring on the same circuit. “The test showed the viability of memory processing functions to operate faster and more efficiently,” ORNL’s Yehuda Braiman said. “This could lead to substantially decreased access energies and access times and allow for more circuits to occupy less space.” Building on the initial design, ORNL’s Braiman, Niketh Nair and Neena Imam continue working on multi-valued memory cell circuits and large arrays of memory cells. Their first step was a ternary memory cell circuit design, which was published in Superconductor Science and Technology.