World’s Smallest DRAM Cell Promises Low-Power Memory in Future Mobile Devices

DRAM memory cells
Schematic representation of the transistor used in a meta-stable dip DRAM (MSDRAM). In the ‘1’ state (shown here), electric charge (holes) is stored in the transistor body, modulating the current that flows through the channel between source and drain. In the ‘0’ state, the holes are removed from the transistor body. Image: Carlos Navarro, University of Granada.

Dynamic random-access memory (DRAM) is everywhere: from desktop computers to portable devices and videogame consoles. In a new paper published in Nature Electronics, we demonstrate the smallest ever built DRAM memory cell, fifty years after its invention. Our new DRAM cells feature potentially low power consumption and an unprecedented small footprint. They could be therefore particularly appealing for implementation in mobile devices or as cache memory.

Limits to scaling storage density with trench capacitors
DRAM usually fulfills the function of the main memory due to its superior storage density and low cost. The high storage density of DRAM stems from the simplicity of its architecture. DRAM memory cells consist of a MOSFET transistor and a capacitor. Their inventor, IBM scientist Robert Dennard, came up with the idea of storing information in form of electric charge on a capacitor controlled by a transistor in the mid-1960s. The different current levels associated with the amount of charge stored on the capacitor would serve to encode the binary logic states 0 and 1. The capacitor must be large enough to store a measurable amount of charge. On the other hand, the need for increased areal storage density limits the growth along the lateral dimensions.  The has left the third dimension as the only way to increase the capacitor size.  That’s why the customary technique consists of fabricating trench capacitors in deep narrow holes in the silicon carrier.

Although DRAM is the main memory of a computer, it is typically not integrated on the CPU chip, but rather provided on separate chips linked with a high-speed bus. Memory on the CPU chip, often referred to as cache memory, is usually fabricated in SRAM technology. SRAM does not need a capacitor and can operate at higher speed than DRAM. The drawback is SRAM’s lower storage density. However, the fabrication technologies for CPU processing and capacitor formation have become very specialized. As a consequence, embedding DRAM on a CPU chip is largely unattractive.

Getting rid of the capacitor in DRAM cells
Over the last two decades, there have been attempts to get rid of the capacitor, thereby further reducing both the footprint and the cost of fabrication of DRAM cells. Removing the capacitor has become almost an imperative in order to push downscaling further. That’s because shrinking the lateral dimensions of the cells without decreasing the amount of charge that can be stored leaves only one avenue open for fabrication, i.e.: making the capacitor “well” even deeper.

In the long term, this represents a bottleneck —not only due to geometrical constraints, but also because charge accumulation at the top of the “well” makes it more challenging to use the entire storage capacity. Storing the charge in the transistor body instead has been identified as the best strategy to further downscaling. Different variants of capacitor-less DRAM cells have been experimentally studied using silicon. But very little attention has been given to similar concepts based on alternative semiconducting materials.

Memory operation down to a gate length of 14 nanometers

In our paper, “Capacitor-less dynamic random-access memory based on a III–V transistor with a gate length of 14 nm,” published in Nature Electronics, we demonstrate the smallest ever built capacitor-less DRAM memory cell featuring a physical gate length of only 14 nanometers. This achievement was possible thanks to a collaboration with scientists from the University of Granada, Spain, as part of the research project “REMINDER” funded by the European Commission. The transistors made at the IBM Research Zurich Lab using the III-V material InGaAs were electrically characterized by our Spanish partners, demonstrating the feasibility of DRAM operation based on the concept of metastable dip RAM (MSDRAM).

This is a single-transistor, capacitor-less DRAM cell, which uses the transistor body as a sort of capacitor in which the electric charge (in this case holes) is stored temporarily. Injection and extraction of the electron holes from the transistor body enables the modulation of the electrostatic behavior of the transistor, thus leading to the two different current levels. III-V materials like InGaAs typically feature smaller bandgaps than silicon which, in principle, offers the potential advantage of operation at significantly lower voltages. This, in turn, translates in potentially much lower power consumption.

DRAM
A TEM image of the InGaAs transistor fabricated at the IBM Research Lab Zurich. The gate length Lg corresponds roughly to the distance between the source and the drain of the transistor. Image: Marilyne Sousa, IBM Research.

In summary, we have demonstrated the feasibility of capacitor-less MSDRAM cells down to a gate length of 14 nanometers. By using the transistor body to store an electron hole population we were able to achieve two distinct current levels corresponding to the binary states 0 and 1. The experimental realization of this memory concept confirmed results obtained by TCAD simulations. Our novel concept using InGaAs provides a promising path toward an aggressive miniaturization of DRAM memory while also reducing power consumption compared with implementations based on silicon. We also see potential for further improvement of this concept regarding performance metrics such as retention time and are confident that viable strategies exist to achieve those improvements.